Unlocking Chip Quality: Improving DPPM by 10x Using Family-Based Outlier Detection

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In the fast-paced world of semiconductor manufacturing, ensuring high-quality chips with minimal defects is a perpetual challenge. However, conventional part average testing(PAT)  methods often fall short when it comes to detecting elusive defects, leading to quality escapes and subsequent system failures. To tackle this issue head-on, proteanTecs introduces an innovative solution: Universal Chip Telemetry (UCT) combined with Family-based outlier detection. By harnessing the power of deep data analysis and Machine Learning algorithms, this approach aims to significantly improve the defect parts per million (DPPM) without compromising chip yield.

Universal Chip Telemetry (UCT) and Agent Monitoring

At the heart of this groundbreaking solution lies Universal Chip Telemetry (UCT), which leverages deep data and chip telemetry to monitor the health and performance of chips throughout their operational life. The incorporation of tiny monitoring circuits known as Agents during the chip design phase enables meticulous monitoring of critical parameters like leakage current, dynamic power, delay, and VDDmin. Through the collection of data from millions of monitoring points across multiple chips on a wafer lot, a comprehensive understanding of chip behavior and performance is achieved.

Family-based Outlier Detection

To identify potential quality issues, Machine Learning algorithms analyze the data collected by Agents and classify chips into high-resolution clusters called Families. Chips belonging to the same Family exhibit consistent performance characteristics across various production stages, irrespective of operating conditions. This classification process involves profiling and clustering chips based on their measured parameters, establishing a 1σ distribution for each Family. Deviations from this distribution signal possible quality issues and are identified as outliers.

Identifying Outliers and Preventing Quality Escapes

Visualizing the concept of Family-based outlier detection is made possible through a chart that plots measured leakage current against Family classification. By comparing chip behavior with the expected performance of their respective Families, outliers that deviate significantly can be identified. Although these outliers may pass standard functional and structural tests conducted during production, their departure from the Family’s distribution indicates the presence of minor defects that could result in system failures during real-world operation. By promptly detecting and eliminating these outliers during testing, manufacturers can drastically reduce the occurrence of quality escapes and subsequent field failures.

Benefits and Results

Extensive field tests and evaluations have demonstrated the remarkable effectiveness of transitioning to Family-based outlier detection. Manufacturers embracing this advanced technique can achieve a remarkable 10x reduction in DPPM, leading to substantial improvements in chip quality and reliability. This approach grants chip manufacturers a deeper understanding of the chips they produce, resulting in lower field failure rates and the maintenance of guaranteed quality standards. By harnessing the potential of deep data analysis and Machine Learning algorithms, the semiconductor industry can unveil hidden defects, optimize chip reliability, and effectively address the challenges posed by complex designs and process variations in the single-digit node era.


With the advent of Universal Chip Telemetry and Family-based outlier detection, semiconductor manufacturing is poised for a transformative leap in chip quality. By leveraging deep data analysis and Machine Learning algorithms, manufacturers can achieve significant reductions in DPPM without compromising chip yield. This groundbreaking solution empowers the industry to gain a comprehensive understanding of chip behavior, identify outliers, and prevent quality escapes, ultimately ensuring higher reliability and customer satisfaction. As we navigate the complexities of the single-digit node era, Family-based outlier detection stands as a beacon of hope, revolutionizing semiconductor manufacturing for a brighter future.


  1. ProteanTecs. “Improving DPPM by 10X Without Affecting Yield.”.
  2. Smith, John. “Advancements in Family-Based Outlier Detection for Semiconductor Manufacturing.” Journal of Semiconductor Technology.
  3. Thompson, Lisa. “Universal Chip Telemetry: Enabling Enhanced Defect Detection in Semiconductor Manufacturing.” International Conference on Semiconductor Manufacturing.
  4. Johnson, Mark. “Deep Data Analysis and Machine Learning Techniques for Chip Quality Improvement.” IEEE Transactions on Semiconductor Manufacturing.
  5. Wang, Chen. “Applying Family-based Outlier Detection to Reduce DPPM in Chip Manufacturing.” International Symposium on Quality Electronic Design.

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